1. Field of the Invention
The present invention relates to a memory cell or storage capacitor and method for forming the memory cell capacitor. More particularly, the present invention relates to a one-step masking and etching technique which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly node to increase the surface area of the storage poly node.
2. State of the Art
A widely-utilized DRAM (Dynamic Random Access Memory) manufacturing process utilizes CMOS (Complimentary Metal Oxide Semiconductor) technology to produce DRAM circuits which comprise an array of unit memory cells, each including one capacitor and one transistor, such as a field effect transistor ("FET"). In the most common circuit designs, one side of the transistor is connected to one side of the capacitor, the other side of the transistor and the transistor gate are connected to external circuit lines called the bit line and the word line, and the other side of the capacitor is connected to a reference voltage that is typically 1/2 the internal circuit voltage. In such memory cells, an electrical signal charge is stored in a storage node of the capacitor connected to the transistor, which opens and closes to charge and discharge the circuit lines of the capacitor.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. The advantages of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. In pursuit of increased miniaturization, DRAM chips have been continually redesigned to achieve ever higher degrees of integration. However, as the dimensions of the DRAM chips are reduced, the occupation area of each unit memory cell of a DRAM chip must be reduced. This reduction in occupied area necessarily results in a reduction of the dimensions of the capacitor, which in turn, makes it difficult to ensure required storage capacitance for transmitting a desired signal without malfunction. However, the ability to densely pack the unit memory cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing if future generations of DRAM chips are to be successfully manufactured.
In order to minimize such a decrease in storage capacitance caused by the reduced occupied area of the capacitor, the capacitor should have a relatively large surface area within the limited region defined on a semiconductor substrate. The drive to produce smaller DRAM circuits has given rise to a great deal of capacitor development. However, for reasons of available capacitance, reliability, and ease of fabrication, most capacitors are stacked capacitors in which the capacitor covers nearly the entire area of a cell and in which vertical portions of the capacitor contribute significantly to the total charge storage capacity. In such designs, the side of the capacitor connected to the transistor is generally called the "storage node" or "storage poly" since the material out of which it is formed is doped polysilicon, while the polysilicon layer defining the side of the capacitor connected to the reference voltage mentioned above is called the "cell poly".
Furthermore, a variety of methods are used for increasing the surface area of the capacitor. These methods include forming the capacitor with various three-dimensional shapes extending from the capacitor. Such shapes include fins, cylinders, and cubes, as well as forming rough or irregular surfaces on these shapes.
FIGS. 7-10 illustrate a prior art technique for forming a capacitor for a memory cell. FIG. 7 illustrates an intermediate structure 200 in the production of a memory cell. This intermediate structure 200 comprises a substrate 202, such as a lightly doped P-type crystal silicon substrate, which has been oxidized to form thick field oxide areas 204 and exposed to implantation processes to form drain regions 208 and a source region 210 of N+ doping. Transistor gate members 212 are formed on the surface of the substrate 202 and span between the drain regions 208 and source region 210. The transistor gate members 212 each comprise a thin gate oxide layer 206 separating a gate conducting layer or wordline 216 of the transistor gate member 212 from the substrate 202. Transistor insulating spacer members 218 are formed on either side of each transistor gate member 212. A lower insulating layer 220 is applied over the transistor gate members 212 and the substrate 202. After application, the lower insulating layer 220 is planarized.
The planarized lower insulating layer 220 is then masked and etched to form a channel therethrough to the source region 210. A bitline 222 is then formed to contact the source region 210 and extend to other source regions (not shown) on the planarized surface 224 of the planarized lower insulating layer 220. An upper insulating layer 226 is then applied over the lower insulating layer 220 and the bitlines 222. After application, the upper insulating layer 226 is planarized.
The planarized upper insulating layer 226 is then masked and etched to form channels through the upper insulation layer 226 and the lower insulating layer 220 to respective drain regions 208. A storage poly 228 is then deposited over the planarized upper insulating layer 226 such that the storage poly 228 extends through the channels to contact the drain regions 208.
As shown in FIG. 8, the storage poly 228 is then masked with a resist layer 230 and etched to separate the storage poly 228 into storage poly nodes 232 (shown in FIG. 9). A capacitor or cell dielectric 234 is deposited over the storage poly nodes 232 and the upper insulating layer 226. A cell poly or plate electrode 236 is then disposed over the capacitor dielectric 234 to form the capacitor 238 of each memory cell, as shown in FIG. 10.
If the surface area of the capacitor 238 needs to be increased, further processing steps would be required to form an irregular or rough surface on the storage poly nodes 232 prior to the addition of the capacitor dielectric 234 and the cell poly electrode 236.
U.S. Pat. No. 5,457,063 issued Oct. 10, 1995 to Park ("the Park patent") teaches a method of increasing the surface area of a capacitor. The Park patent illustrates a prior art method of first etching recesses in the polysilicon layer to form the storage poly nodes, then again etching the polysilicon layer to separate individual storage poly nodes. The Park patent teaches using the same prior art two step method to form the storage poly nodes, but also forms polysilicon sidewalls to exploit the empty space around the periphery of the storage poly node. Although both the prior art method and the method of the Park patent increase the surface area of a capacitor, each require numerous processing steps to achieve this goal. The additional process steps result in increased production costs which, in turn, result in increased semiconductor chip costs.
Therefore, it would be advantageous to develop a technique for forming a high surface area capacitor, while using inexpensive, commercially-available, widely-practiced semiconductor device fabrication techniques and apparatus without requiring such additional processing steps.